1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to fabricating a MOSFET transistor having a polysilicon gate conductor with silicide formed simultaneously on top and sidewall surfaces of the gate conductor and on junction regions adjacent to the gate conductor without shorting the conductor to adjacent junctions or consuming the shallow junction regions.
2. Description of the Related Art
Fabrication of an integrated circuit involves numerous processing steps. Generally a dielectric material is formed upon a substrate, such as a monocrystalline silicon wafer. The gate conductor material is then formed upon the dielectric and subsequently patterned to expose the dielectric material deposited upon predetermined impurity regions residing in the semiconductor substrate. Patterning the gate conductor typically involves lithography in which a protective mask, photoresist, has been exposed to light and removed in the areas over the impurity regions prior to an etch process. Ion implantation may then be performed to form lightly doped drain (xe2x80x9cLDDxe2x80x9d) and source/drain (xe2x80x9cS/Dxe2x80x9d) junctions in the impurity regions. Rapid thermal annealing is typically utilized to complete the formation of the LDD and source/drain junctions. After the impurity regions have been placed into a semiconductor substrate and gate regions defined upon the substrate, an interlevel dielectric may be formed across the topography to isolate the gate regions and the impurity regions. Processing steps may then be performed to create ohmic contacts which connect the gates and/or junctions to other devices in the integrated circuit.
Integrated circuits often employ active devices known as transistors. A transistor includes a pair of impurity regions, or junctions, spaced laterally apart by a gate conductor. The gate conductor is dielectrically spaced above a semiconductor substrate within which the junctions reside. The junctions contain dopants which are opposite in type to the dopants residing within a channel region of the substrate interposed between the junctions. The gate conductor typically comprises polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) which is rendered conductive by implanting dopants therein. Polysilicon can withstand relatively high temperatures. Therefore, a polysilicon gate conductor may be formed prior to performing high-temperature anneal steps, such as the post-implant anneal of the junctions. As such, the gate conductor may be patterned before the source and drain junctions are formed and annealed. In fact, the gate conductor is commonly used as a channel region mask during the formation of the source and drain junctions.
One of the disadvantages of using polysilicon as the gate conductor material, however, is that it inherently has a significantly higher resistivity than metals, such as aluminum. Therefore, the propagation delay of an integrated circuit employing a polysilicon gate conductor may be longer than desired. Consequently, the operational frequency that may be achieved by a circuit employing a polysilicon gate conductor may be somewhat limited. However, forming silicide upon a polysilicon gate conductor helps lower the sheet resistance of the gate conductor. Silicide formed upon polysilicon is generally referred to as polycide. A salicidation process involves depositing a refractory metal across the semiconductor topography, and then reacting the metal only in regions where a high concentration of silicon atoms are present. Therefore, dielectric sidewall spacers, formed on the sidewalls of a gate conductor prior to salicidation, prevent refractory metal from contacting, and hence reacting with, the sidewalls of the gate conductor. Absent the sidewall spacers, silicide may form upon the sidewall surfaces of the silicon-based gate conductors and undesirably short the gate conductors to adjacent junctions. The resulting silicide is, therefore, self-aligned to regions of high concentrations of silicon and is generally referred to as salicide. In this manner, salicides may be formed simultaneously upon the junctions and the top surface of the polysilicon gate conductors.
FIG. 1 depicts a transistor 10 having salicides formed simultaneously upon the junctions and the top surface of the polysilicon gate conductor. A polysilicon gate conductor 12 is spaced above a semiconductor substrate 14 by a gate dielectric 16. LDD regions 18 in the semiconductor substrate 14 extend laterally from opposed sidewalls 20 of the polysilicon gate conductor 12. The polysilicon gate conductor 12 is laterally surrounded by dielectric sidewall spacers 22 formed on opposed sidewalls 20 of the polysilicon gate conductor 12. The top of the polysilicon gate conductor 24 and the top of the junction regions 26 have been converted to silicide 28. Source/drain regions 30 in the semiconductor substrate 14 are spaced from the polysilicon gate conductor 12 by a width of the dielectric sidewall spacers 22.
As the dimensions of modern transistors shrink to accommodate the high demand for faster, more complex integrated circuits, the width of the transistor gates must also shrink. Consequently, a smaller surface area of the polysilicon gate conductor may be exposed to salicidation. Since silicide that is formed on the polysilicon gate conductor reduces the overall gate resistance, a greater thickness of the polysilicon may be converted to silicide to obtain an acceptable resistivity. Unfortunately, the thickness of polysilicon that may be converted to salicide is limited in conventional salicidation processing in which silicides are formed simultaneously on the gate conductor and the junctions of the transistor. As the dimensions of the transistors shrink, in addition to the width of the gate conductor, the depth of the source/drain junctions decreases. If a salicide process completely consumes a relatively shallow junction and penetrates into the substrate underneath the junction, a phenomenon known as xe2x80x9cjunction spikingxe2x80x9d may occur. Junction spiking may undesirably cause the junction to exhibit large current leakage or cause the circuit to electrically short. Therefore, in order to prevent excessive consumption of shallow junctions, the thickness of the salicide formed on the junctions must be limited. Consequently, gate salicides formed simultaneously with junction salicides must also be of limited thickness.
Another disadvantage of polycide gate conductors is geometry-dependent resistivity. As the width of transistor gates is reduced, polysilicon gate conductors exhibit undesirable increases in resistivity. It has been theorized that regions of high resistivity polysilicon, in which mobile carriers become easily trapped, exist in the vicinity of the grain boundaries characteristic of polysilicon films. As these regions become comparable in size to the overall length of the polysilicon gate conductor, insufficient quantities of silicon may be available for the formation of high quality suicides. When such a condition occurs, the formation rate and quality of silicides formed on the upper surface of short-length polysilicon gate conductors may drop below the formation rate and quality of suicides formed on wider polysilicon structures. The increased resistivity exhibited by short-length gate conductor polycides results in an increased gate contact resistance, which reduces the speed of the transistor. Furthermore, geometry-dependent silicide resistivity is undesirable because semiconductor devices and processes are almost universally designed and simulated under the assumption that silicide resistivity will not exhibit a geometric dependence.
Accordingly, it would be advantageous to develop a salicidation process in which a larger portion of the polysilicon gate could be converted to silicide without shorting the conductors to adjacent junctions or consuming shallow source/drain junctions.
The problems outlined above are in large part solved by a transistor having silicide structures on a portion of the sidewalls of a gate conductor, and a method for fabricating this transistor. That is, a transistor is provided in which a substantial portion of a polysilicon gate conductor may be converted to silicide at the same time that silicide may be formed on exposed portions of the semiconductor substrate. Opposed sidewalls of the polysilicon gate conductor are surrounded by dielectric sidewall spacers. An upper surface of the dielectric sidewall spacers is lower than an upper surface of the polysilicon gate conductor thereby exposing a portion of the sidewall surfaces of the polysilicon gate conductor. In some embodiments, the height of exposed portion of the sidewall surfaces of the polysilicon gate conductor may be about two-thirds of the total gate conductor height. For example, a distance along the outer lateral surface of the dielectric sidewall spacers may be provided in order to sufficiently prevent silicide short-circuiting of the gate to the source/drain regions. In an embodiment, a distance of about 500 xc3x85 may be suitable for this purpose. Larger or smaller dielectric sidewall spacers may be appropriate in some embodiments, however, depending on the particular transistor length. A substantial portion of the polysilicon gate conductor, including the top of the gate conductor and the exposed portion of the sidewall surfaces, may then be subjected to a salicidation process. In this process, salicide structures may also be formed on the exposed portions of the semiconductor substrate. Therefore, using conventional salicidation processing a polysilicon gate conductor with lower resistivity may be formed while consumption of the junction regions or shorting of the gate conductor to the junction regions may be avoided.
In addition to a transistor as described above, a method of forming a transistor is contemplated herein. According to an embodiment, a polysilicon gate conductor may be formed above a gate dielectric layer formed upon a semiconductor substrate. The gate conductor is laterally bound between a pair of opposed sidewall surfaces. An LDD implant may be self-aligned to the opposed sidewall surfaces of the gate conductor to form LDD regions within the substrate spaced apart by a channel region. The gate conductor serves as a mask above the underlying channel region during the LDD implant. The dopant species used for the LDD implant is opposite in type to the dopant species residing in the channel region. Rapid thermal annealing is utilized to complete the formation of the LDD junctions.
A dielectric layer, such as silicon dioxide, may be formed on the polysilicon gate conductor and the gate dielectric. The dielectric layer may then be subjected to an anisotropic etch process in which first dielectric sidewall spacers are formed laterally adjacent the opposed sidewall surfaces of the polysilicon gate conductor. The etch process may remove a portion of the dielectric sidewall material such that the upper surface of the first dielectric sidewall spacers is lower than the upper surface of the polysilicon gate conductor. A portion of the polysilicon gate conductor sidewall, including the polysilicon gate conductor sidewall above the upper surface of the first dielectric sidewall spacer, is thereby exposed for subsequent processing. For example, in an embodiment, the etch process may remove a portion of the dielectric sidewall spacer such that the height of the exposed portion of the sidewall surfaces of the polysilicon gate conductor is about two-thirds of the total gate conductor height. Additionally, a distance along the outer lateral surface of the dielectric sidewall spacers may be provided in order to sufficiently prevent silicide short-circuiting of the gate to the source/drain regions. The gate dielectric over the junction regions may also be removed during the above etch process.
A refractory metal, such as cobalt or titanium, may then be deposited over the entire semiconductor substrate. The refractory metal may be heated to promote cross-diffusion and reaction between the metal atoms and silicon atoms of the polysilicon gate conductor and the junction regions. The refractory metal may, for example, be heated to a temperature of 600 to 800xc2x0 C. for approximately 15 to 60 seconds using a technique known as rapid thermal processing (xe2x80x9cRTPxe2x80x9d). In this manner, a silicide comprising cobalt silicide or titanium silicide may be formed on the top of the gate conductor, the exposed portions of sidewalls of the gate conductor, and the junction regions in the semiconductor substrate adjacent the gate conductor. As such, the dielectric sidewall spacers are thick enough to prevent silicide bridging between the gate conductor and the junction regions which may cause shorting of the circuit, and salicidation may be terminated prior to consumption of the junctions. Any unreacted metal may then be removed.
Prior to forming the source/drain regions, a second dielectric sidewall spacer may be formed laterally adjacent the first dielectric sidewall spacers and exposed portions of the gate conductor sidewalls. A dielectric layer, such as silicon nitride, may be formed on the polysilicon gate conductor and the semiconductor substrate. The dielectric layer may then be subjected to an anisotropic etch process in which second dielectric sidewall spacers are formed laterally adjacent the exposed portions of the sidewall surfaces of the polysilicon gate conductor and the first dielectric sidewall spacers. A source/drain implant may then be self-aligned to the outer lateral edges of the second dielectric sidewall spacers.
A second ion implantation process may then be performed in order to form the source/drain regions. Rapid thermal annealing is utilized to complete the formation of the source/drain junctions. The S/D implant may be performed using the same type of dopant species as that used for the LDD implant, but at a higher does and energy than the LDD implant. Therefore, source and drain regions may be placed within the substrate a lateral spaced distance from the gate conductor. The LDD regions may be retained only in the semiconductor substrate beneath the sidewall spacers. An additional insulating material may now be deposited across the semiconductor substrate to complete the formation of a transistor.
In an alternative embodiment, second dielectric sidewall spacers may be formed prior to formation of the silicide and implantation of the source/drain regions. Implantation of the source/drain regions may then be performed prior to salicidation of the exposed portions of the polysilicon gate conductor and the exposed portions of the semiconductor substrate. The second dielectric sidewall spacers may then be removed by an etch process prior to salicide processing.
Alternatively, the formation of a second dielectric sidewall spacer may be eliminated in the above embodiment. Therefore, the source/drain implant may be self-aligned to the outer lateral edges of the first dielectric sidewall spacers. LDD regions may be located in the semiconductor substrate between the outer lateral edges of the gate conductor and the first dielectric sidewall spacers. Silicide may then be formed on exposed portions of the semiconductor substrate, including only the source/drain regions, because the LDD regions are substantially masked during salicidation by the first dielectric sidewall spacers. In this embodiment, silicide may also be formed prior to or subsequent to implantation of the source/drain regions.
In an alternative embodiment, LDD regions may be formed subsequent to the formation of the first dielectric sidewall spacers. The LDD regions may, therefore, be self-aligned to the outer lateral edges of the of the first dielectric sidewall spacers and laterally spaced from the gate conductor. Salicidation may then be performed as described in the above embodiment to form silicide on the top of the gate conductor, on the partially exposed sidewalls of the gate conductor, and on the exposed regions of the semiconductor substrate. In this embodiment, salicidation may also be performed as described above prior to forming the LDD regions in the semiconductor substrate. Second dielectric sidewall spacer formation and implantation of the source/drain regions may then be performed to complete the formation of the transistor.
In an additional embodiment, silicide may be formed on the gate and the junctions after the LDD and source/drain junctions have been formed. LDD regions may be formed in the semiconductor substrate laterally adjacent the polysilicon gate conductor. First dielectric sidewall spacers having an upper surface that is lower than an upper surface of the polysilicon gate conductor may then be formed on the opposed sidewall surfaces of the polysilicon gate conductor. The LDD regions may also be formed in the semiconductor substrate subsequent to first dielectric sidewall spacer formation thereby providing LDD regions that are laterally spaced from the gate conductor. The second dielectric sidewall spacers may then be formed as described in an above embodiment. An overetch step may be included to provide an upper surface of the second dielectric sidewall spacers that is lower than an upper surface of the polysilicon gate conductor thereby exposing a portion of the gate conductor sidewalls. Implantation of the source/drain regions may then be performed as described in an above embodiment. In embodiments for which the LDD regions are formed adjacent the gate conductor, the source/drain implants may also be performed after formation of the first dielectric sidewall spacers and prior to second dielectric sidewall spacer formation. Salicidation of the gate and source/drain materials may then be performed as described in the above embodiments to form silicide on the top of the gate conductor top, on the partially exposed sidewalls of the gate conductor, and on the source and drain regions.
In addition to the method described above, a transistor is contemplated herein in which a substantial portion of a polysilicon gate conductor has been converted to silicide. In an embodiment, a polysilicon gate conductor is spaced above a semiconductor substrate by a gate dielectric layer. LDD regions in the semiconductor substrate may extend laterally from the polysilicon gate conductor sidewalls. LDD regions in the semiconductor substrate may also be laterally spaced from the polysilicon gate conductor. The polysilicon gate conductor may be laterally surrounded by first dielectric sidewall spacers formed on opposed sidewalls of the polysilicon gate conductor. The first dielectric sidewall spacers have an upper surface that is lower than an upper surface of the polysilicon gate conductor such that exposed portions of the polysilicon gate conductor sidewalls are interposed between the two upper surfaces. Silicide may be formed on the upper surface of the polysilicon gate conductor and on the exposed portions of the polysilicon gate conductor sidewalls. Silicide may also be formed on exposed portions of the semiconductor substrate including upper surfaces of the source/drain and LDD regions. Alternatively, silicide may be formed on the exposed portions of the semiconductor substrate including only the upper surfaces of the source/drain regions. Second dielectric sidewall spacers may laterally extend from the first dielectric sidewall spacers and the exposed portions of the polysilicon gate conductor sidewalls. Second dielectric sidewall spacers may also have an upper surface that is lower than an upper surface of the polysilicon gate conductor such that exposed portions of the polysilicon gate conductor sidewalls are interposed between the upper surfaces of the first and second dielectric sidewall spacers. Source/drain regions in the semiconductor substrate may extend laterally from outer surfaces of the second dielectric sidewall spacers. Additionally, source/drain regions in the semiconductor substrate may extend laterally from outer surfaces of the first dielectric sidewall spacers.
The formation of silicide on a portion of the sidewalls of the gate conductor, in addition to the top surface of the gate conductor, may provide several advantages over standard salicidation processing. Exposing a greater surface area of the polysilicon gate conductor to salicidation may provide a polysilicon gate conductor with adequate resistivity to meet the performance requirements of modern transistors despite the reduced dimensions of the gates. Formation of silicide on a portion of the sidewalls of the gate conductor may also serve to strengthen the polysilicon gate conductor material. As the length of MOSFET transistors approaches 100 xcexcnm and below, the crystalline structure of the gate conductor may be only a few grains wide. Processing conditions, such as temperature changes, pressure waves from ultrasonic baths and exposure to aggressive chemicals, may cause the thin polysilicon gates to break at weak crystalline points. By converting a larger percentage of the gate conductor to silicide, the gate conductor may be less susceptible to damage caused by subsequent processing.
By forming salicide on a portion of the sidewalls of the gate conductor, in addition to the top surface, salicide may also be simultaneously formed on the junction regions of the transistor without consuming the entire thickness of the junctions. As modem transistors shrink, the source/drain junctions may also become shallower. Therefore, the capability to simultaneously form an adequate amount of salicide on the gate conductor in order to achieve the requirements for the gate resistivity without consuming the shallower junctions will become more difficult and more critical in the successful fabrication of modem transistors. Very shallow source/drain junctions may also become difficult to form using conventional implantation equipment. Silicide formation on the source/drain regions may serve to enable the formation of very shallow junctions while eliminating the need to continuously lower the implantation energy. A process involving higher implantation energy will be better controlled and make use of existing equipment for future generations of transistor devices.
Successfully forming adequate silicide on the gate conductor and junction regions prior to ion implantation in the junction regions may provide additional advantages. For example, implanting the source/drain regions after silicide formation may eliminate a substantial loss of dopant from the surface of the junction regions during subsequent rapid thermal processing. Additionally, silicide that is formed on the sidewalls of a gate conductor prior to implantation may be used as a sidewall spacer for subsequent implantation processes. The thickness of the silicide formation on the sidewalls of the gate conductor may be controlled by varying the metal to silicide formation/conversion temperatures. Therefore, by controlling the phase transition, for example from Co2Si to CoSi or from CoSi to Co2Si, the thickness of the silicide may also be controlled. In this manner, the placement of the LDD and the source/drain regions by subsequent implantation in the semiconductor substrate may be adjusted. Thus, an advanced process control strategy, in which the phase transition during the salicidation process is strategically controlled, may be used to control the depth and the placement of the LDD and source/drain formation according to the critical dimension criteria for a particular transistor.